a. Field of the Invention
This invention relates to a keyboard interface, and more particularly, to a serial keyboard interface system to prevent the erroneous transmission of keyboard data due to noise.
b. Background Art
There has been proposed a keyboard system in which a keyboard and a data processing unit are connected through a data line and a clock line so as to transmit keyboard out codes bit-serially through the data line and to transmit a keyboard out clock signal through the clock line. The keyboard out codes are transmitted in a 9-bit frame consisting of a leading start bit and the following 8-bit serial scan code identifying a key position. On the data processing unit side, there is provided a 9-stage serial-parallel shift register connected to the data line and clock line. The bits of the frame received are loaded successively from lowest order or least significant stage of the serial-parallel shift register under the control of the clock signal. The completion of the receipt of the 9-bit frame is indicated when the start bit appears at the highest order or most significant stage.
The start bit from the highest order stage causes an interruption to request the read-in of the scan code located in the shift register into the data processing unit, and also signals to the keyboard that additional keyboard data cannot be sent until the read-in process is completed.
This keyboard system is very simple because the keyboard data can be sent by the use of a single data line and a single clock line, and further the keyboard has the advantage of being operated at the pace of its own clock independently of the clock of the data processing unit.
It was found, however, that this keyboard causes false operation due to noise when a low cost stretch cable without shield is used as a cable for connecting the keyboard with the data processing unit. Static discharge typical of external disturbance introduces noise pulses on the cable. The noise pulse may be induced on either or both the data and clock lines. When the data signal is sampled in response to the transitions of the clock signal for loading into the shift register, a bit error may be caused if the noise pulse on the data line is sampled. However, this bit error may be detected, for example, by parity check.
On the other hand, when the noise pulse is induced on the clock line, the same data bit is sampled twice by the normal clock signal and the noise pulse. This leads to false receipt of 9 bits of a frame by the serial-parallel shift register before the 9-bit transmission from the keyboard is completed, resulting in dropout of the 9th bit. Since the number of binary 1's is unchanged when the last bit dropped out is binary 0 and the data bit sampled twice is binary 0 and when the last bit is binary 1 and the data bit sampled twice is binary 1, this data error cannot be detected by parity check. The data error is also caused when clock pulses are counted in response to the transitions of the clock signal until a predetermined number of bits of a frame is reached, which indicates the end of a frame. In this case, counting is made twice in one clock cycle due to noise, causing similar erroneous transmission.
Although such data error due to noise pulses may be prevented by the use of a shielded cable, such a cable is very expensive and it is desired to prevent such data error when a low cost cable without shield is used.